The present invention is directed to the use of ordered polymers as a substrate material for the preparation of printed wire boards (PWB). Major advances have recently been made in progressing from conventional dual in-line packages (DIP) to direct surface mounting packages (DSM).
DIPs are generally limited in size by the large pins which must be mounted through holes in the circuit board. DSMs can be mounted on both sides of the boards and have both more and smaller input/output (I/O) connections.
The full benefits of increased speed and reduced size and weight in PWBs have not yet been realized because interconnection of DSM devices has not kept pace with I/O density and the reduction in size possible with leadless perimeter and grid array packages.
One of the major problems of using leadless ceramic chip carriers in advanced avionics (VHSIC and VLSI) applications is the mismatch between the coefficient of thermal expansion (CTE) of alumina chip carriers (6.4 ppm/.degree.C.) and conventional glass/epoxy substrates (12 to 17 ppm/.degree.C.). This mismatch results in work-hardening and cracking of solder joints which attach the DSM chips to the substrate.
Thermal cycles as extreme as -65 to +125C. may be encountered and are known to cause solder failure and other damage. As demonstrated herein, ordered polymer films can solve this problem because they can be matched to the ceramic CTE. Moreover, ordered polymers have excellent dielectric properties, and thin biaxially oriented films can be produced which show significant advantages over other high performance substrates.
Fiber reinforced substrates (Kevlar and graphite reinforcement) are being developed to match the ceramic CTE, but these materials have drawbacks. Fibers must be woven into a fabric, or cross-plied resulting in increased thickness and anisotropy at a relatively large scale (fiber tow diameters are about 0.002 in., minimum fabric thickness is about 0.0045 in.). Additional problems of high dielectric constant and costly manufacturing are discussed below.
Copper-Invar-Copper (CIC) laminated foils can provide matched CTE, but these materials are relatively heavy (this precludes their use in avionics applications) and require insulation on the surface and inside vias (holes which connect multilayers).
Ceramic substrates are not considered because their brittleness and high dielectric constant (9-10) rule them out. Recently, Hitachi, Inc., has reported low CTE polyimide film, for example Numota et al., "Chemical Structures and Properties of Low Thermal Polyimides," p. 492-510, Proceeding of the Second International Conference on Polyimides, Society of Plastics Engineers, Inc., (1985), but the material is still in the early development stages and sample quantities have not been evaluated.
Polyimide films also suffer from high moisture absorption (5 percent by weight) which degrades dielectric performance and causes hygroscopic expansion.
Advanced computer systems are dependent upon very high density circuit boards having a large number of internal plane, many conducting circuit lines, and a multitude of holes formed in close proximity to the internal conductors. Using present materials and conductor technologies, minimum conductor widths of 3 mil and 3 mil spacings are possible at best. Higher density PWBs are needed to meet the increasing density of circuits packages on semiconductor devices and modules.